Low temperature poly-silicon (LTPS) has a high electron mobility ratio, and thereby it can effectively reduce the area of thin film transistor (TFT) elements, increase the aperture ratio of pixels, and enhance the display lightness of panels, but simultaneously lowers the entire power consumption, so that the manufacturing cost of panels is substantially reduced, so now LTPS has become a research hot point in a field of liquid crystal displays.
In a conventional design of LTPS, mask processes of an array substrate are more complex, generally about ten mask processes are required, so that the production capacity of the products is substantially lowered. Furthermore, since the processes are more complex, the yield rate thereof is also lower, so that LTPS is difficult to promote, and is only applied in small size products.
Refer now to FIG. 1 which is a structural schematic view of an array substrate according to a conventional technology. As shown in FIG. 1, a manufacturing method of a conventional array substrate comprises the following steps of: forming a light-shading layer 11 on a substrate 10; forming a buffer layer 12 on the light-shading layer 11; forming a semiconductor layer 13 on the buffer layer 12, wherein the semiconductor layer 13 has to be treated with a heavy doped and a light doped by exposing and developing methods; forming a first insulation layer 14 on the semiconductor layer 13; forming a first metal layer 15 on the first insulation layer 14; forming a second insulation layer 16 on the first metal layer 15; forming a second metal layer 17 on the second insulation layer 16; forming a flat layer 18 on the second metal layer 17; forming a first transparent conductive layer 101 on a portion of the flat layer 18 which does not correspond to an area of source electrodes and drain electrodes, wherein through a via, the first transparent conductive layer 101 is connected with a portion of the second metal layer which is not of the source electrodes and the drain electrodes; forming a second transparent conductive layer 102 on a portion of the flat layer 18 which corresponds to the area of the source electrodes and the drain electrodes, wherein the second transparent conductive layer 102 is connected with the source electrodes and the drain electrodes; and forming a third second insulation layer 19 between the first transparent conductive layer 101 and the second transparent conductive layer 102.
In the above processes, the manufacturing processes of the light-shading layer, the semiconductor layer, the heavy doping and the light doping, the flat layer, the source electrodes and the drain electrodes, the second insulation layer, the first transparent conductive layer, the third insulation layer, and the second transparent conductive layer all need masks for processing exposing, so that the processes are more complex, and the processing requirement is higher, causing the manufacturing cost to also be higher.
Hence, it is necessary to provide an array substrate and a manufacturing method thereof which solves the problems existing in the conventional technologies.